The present invention relates to methods of manufacturing improved performance, narrow width, high operating speed, CMOS devices comprised of one or more of each of NMOS and PMOS transistors, on strained lattice semiconductor substrates, and to improved CMOS devices obtained thereby. More specifically, the present invention relates to methods for fabricating such devices wherein the stress level within the strained lattice semiconductor layer of the NMOS and PMOS portions of the device is differentially adjusted to maximize the respective drive currents.
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 xcexcm and below, e.g., such as 0.15 xcexcm and 0.12 xcexcm, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor materials and manufacturing techniques.
A conventional approach for forming a plurality of active devices in or on a common semiconductor substrate, e.g., as in the case of forming CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency, involves division of a starting material, i.e., a semiconductor substrate of suitable characteristics, into active regions where the transistors are to be formed, and field dielectric regions that electrically isolate adjacent active regions.
According to current technology utilizing conventional crystalline semiconductor wafers as substrates, the starting material may, for example, comprise a lightly p-doped epitaxial (xe2x80x9cepixe2x80x9d) layer of silicon (Si) grown on a heavily-doped, crystalline Si substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of the very thin epi layers, i.e., several xcexcm thick, is made possible by performing the isolation processing by means of shallow trench isolation (xe2x80x9cSTIxe2x80x9d) techniques rather than by high temperature local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d) technology. The STI technique advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, and critical for fabrication of devices with design rule of 0.25 xcexcm and below, STI allows for closer spacing of adjacent active areas by avoiding the xe2x80x9cbird""s beakxe2x80x9d formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Recently, there has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed xe2x80x9cstrained siliconxe2x80x9d.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Sixe2x80x94Ge buffer layer several microns thick, which Sixe2x80x94Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Sixe2x80x94Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Sixe2x80x94Ge) comprised of atoms which are spaced further apart, they xe2x80x9cstretchxe2x80x9d to align with the underlying Si and Ge atoms, thereby xe2x80x9cstretchingxe2x80x9d or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
However, a problem exists with respect to the design and fabrication of optimal performance CMOS devices comprised of at least one pair of narrow-width (W) PMOS and NMOS transistors less than about 1 xcexcm wide utilizing strained lattice semiconductor substrates. Specifically, it has heretofore been difficult to manufacture narrow-width CMOS devices based on strained lattice semiconductor substrates wherein the drive currents of the PMOS and NMOS transistor components thereof are simultaneously maximized. Consider the following apparent competing characteristics or tendencies of narrow-width PMOS and NMOS transistors:
(1) when PMOS and NMOS transistors are fabricated with narrow widths (i.e.,  less than 1 xcexcm) utilizing STI methodology for segmentation of the substrate into active regions where the transistors are to be formed, a compressive stress is exerted on the upper stratum or layer of the adjacent active device regions of the segmented semiconductor substrate spaced apart by the STI region, arising from the insulative material, typically a silicon oxide, filling the STI trench. As a consequence, the drive current of a narrow width PMOS transistor fabricated on or within an active device area subject to such compressive stress is increased, relative to a similar-dimensioned PMOS transistor formed on or within an unstressed semiconductor substrate, whereas the drive current of a narrow width NMOS transistors fabricated on or within the active device area subject to such compressive stress is decreased, relative to a similar-dimensioned NMOS transistors formed on or within an unstressed semiconductor substrate; and
(2) the drive current of a PMOS transistor fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on Sixe2x80x94Ge, is decreased, relative to a similar dimensioned PMOS transistor formed on or within an unstressed semiconductor substrate, whereas the drive current of an NMOS transistor fabricated on or within a tensilely stressed active device area is increased, relative to a similar-dimensioned NMOS transistor formed on or within an unstressed semiconductor substrate.
Accordingly, and in view of the above-described apparent competing characteristics or tendencies of PMOS and NMOS transistors, there exists a need for improved semiconductor design and manufacturing methodology for fabricating CMOS devices on strained lattice semiconductor substrates comprised of narrow-width constituent PMOS and NMOS transistors, which methodology recognizes the above competing effects on the PMOS and NMOS drive currents. Moreover, there exists a need for improved methodology for CMOS device fabrication on strained lattice semiconductor substrates which is fully compatible with conventional process flow for automated manufacturing at rates consistent with the requirements for economic competitiveness.
The present invention, wherein the level of tensile stress in the strained semiconductor layer segments forming active regions for PMOS and NMOS transistors are differentially adjusted (i.e., maximized or minimized) by thickness variation thereof, to maximize the drive currents of both transistor types, effectively eliminates, or at least minimizes, disadvantageous unbalanced drive current performance of the PMOS and NMOS transistors arising from the above-described apparent competing characteristics or tendencies. As a consequence, the inventive methodology facilitates design and manufacture of high speed, high performance, reduced power consumption CMOS devices utilizing strained semiconductor technology. Further, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various MOSFET-based semiconductor devices and/or components which require use of strained semiconductor technology for enhancement of device speed and reduced power consumption.
An advantage of the present invention is an improved method for manufacturing a semiconductor device comprising a strained lattice semiconductor layer.
Another advantage of the present invention is an improved method for manufacturing a MOS transistor device comprising a strained lattice semiconductor layer.
Yet another advantage of the present invention is an improved method for manufacturing a CMOS device comprising a strained lattice semiconductor layer, wherein the drive currents of the component PMOS and NMOS transistors are maximized.
Still another advantage of the present invention is an improved semiconductor device comprising a strained lattice semiconductor layer.
A further advantage of the present invention is an improved MOS transistor device comprising a strained lattice semiconductor layer.
A still further advantage of the present invention is an improved CMOS device comprising a strained lattice semiconductor layer, wherein the drive currents of the component PMOS and NMOS transistors are maximized.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer, and
(b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer.
According to embodiments of the present invention, step (b) comprises forming the at least one MOS transistor as a PMOS transistor or an NMOS transistor having a narrow width less than about 1 xcexcm; and according to certain embodiments of the invention, step (a) comprises providing a semiconductor substrate wherein the upper, tensilely strained lattice semiconductor layer has a pre-selected initial thickness; and step (b) comprises forming the at least one MOS transistor on or within the tensilely strained lattice semiconductor layer as a PMOS transistor, wherein the forming comprises a step of regulating the drive current of the PMOS transistor by reducing the thickness of the tensilely strained lattice semiconductor layer from the pre-selected initial thickness to a pre-selected final thickness, or step (a) comprises providing a semiconductor substrate wherein the upper, tensilely strained lattice semiconductor layer has a pre-selected initial thickness; and step (b) comprises forming the at least one MOS transistor on or within the tensilely strained lattice semiconductor layer as an NMOS transistor, wherein the forming comprises a step of regulating the drive current of the NMOS transistor by increasing the thickness of the tensilely strained lattice semiconductor layer from the pre-selected initial thickness to a pre-selected final thickness.
In accordance with a particular embodiment of the present invention:
step (a) comprises providing a semiconductor substrate wherein the upper, tensilely strained lattice semiconductor layer has a pre-selected initial thickness; and
step (b) comprises steps of:
(b1) segmenting the substrate into at least one pair of adjacent active device areas separated by isolating means; and
(b2) forming a CMOS device comprising at least one pair of PMOS and NMOS transistors in the at least one pair of adjacent active device areas; wherein the drive current of the PMOS transistor is maximized by reducing the thickness of the tensilely strained lattice semiconductor layer of the respective active device area from the pre-selected initial thickness to a pre-selected final thickness, and the drive current of the NMOS transistor is maximized by increasing the thickness of the tensilely strained lattice semiconductor layer of the respective active device area from the pre-selected initial thickness to a pre-selected final thickness or by maintaining the thickness of the tensilely strained lattice semiconductor layer of the respective active device area at the pre-selected initial thickness.
According to embodiments of the present invention, step (a) comprises segmenting the substrate into the at least one pair of adjacent active device areas separated by shallow trench isolation (STI) means; and step (b) comprises reducing or increasing the thickness of the tensilely strained lattice semiconductor layer of the respective active device areas from the pre-selected initial thickness to the pre-selected final thickness by means of a semiconductor material removal or deposition process which, by itself, does not affect the tensile stress of the tensilely strained lattice semiconductor layer, whereby obtainment of device performance enhancements attributed to the tensilely strained lattice semiconductor layer is not compromised.
In accordance with certain embodiments of the present invention, step (a) comprises providing a semiconductor substrate including an upper, tensilely strained, crystalline silicon (Si) semiconductor layer lattice-matched to a lower, unstressed, crystalline silicon-germanium (Sixe2x80x94Ge) layer; and step (a) may further comprises providing the semiconductor substrate with a crystalline Si layer or wafer beneath the lower, unstressed, crystalline silicon-germanium (Sixe2x80x94Ge) layer.
Another aspect of the present invention is a semiconductor device, comprising:
(a) a semiconductor substrate including an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and
(b) at least one MOS transistor formed on or within the tensilely strained lattice semiconductor layer, wherein the drive current of the at least one MOS transistor is regulated to a pre-selected value by adjustment of the thickness of the tensilely strained lattice semiconductor layer.
According to certain embodiments of the present invention, the at least one MOS transistor is a PMOS transistor or an NMOS transistor having a narrow width less than about 1 xcexcm; and according to particular embodiments, the at least one MOS transistor is a PMOS transistor and the drive current thereof is regulated to the pre-selected value by reducing the thickness of the tensilely strained lattice semiconductor layer from a pre-selected initial thickness to a pre-selected final thickness, or the at least one MOS transistor is an MMOS transistor and the drive current thereof is regulated to the pre-selected value by increasing the thickness of the tensilely strained lattice semiconductor layer from a pre-selected initial thickness to a pre-selected final thickness.
In accordance with further embodiments of the present invention, the semiconductor substrate is segmented into at least one pair of adjacent active device areas separated by isolating means; and the semiconductor device is a CMOS device comprising at least one pair of PMOS and NMOS transistors formed in the at least one pair of adjacent active device areas; wherein the drive current of the PMOS transistor is maximized by reducing the thickness of the tensilely strained lattice semiconductor layer of the respective active device area from a pre-selected initial thickness to a pre-selected final thickness, and the drive current of the NMOS transistor is maximized by increasing the thickness of the tensilely strained lattice semiconductor layer of the respective active device area from a pre-selected initial thickness to a pre-selected final thickness or by maintaining the thickness of the tensilely strained lattice semiconductor layer of the respective active device area at a pre-selected initial thickness.
According to particular embodiments of the present invention, the substrate is segmented into the at least one pair of adjacent active device areas by shallow trench isolation (STI) means, and the thickness of the tensilely strained lattice semiconductor layer of the respective active device areas is reduced or increased from the pre-selected initial thickness to the pre-selected final thickness by means of a semiconductor material removal or deposition process which, by itself, does not affect the tensile stress of the tensilely strained lattice semiconductor layer, whereby obtainment of device performance enhancements attributed to the tensilely strained lattice semiconductor layer is not compromised.
In accordance with certain embodiments of the present invention, the semiconductor substrate includes an upper, tensilely strained, crystalline silicon (Si) semiconductor layer lattice-matched to a lower, unstressed, crystalline silicon-germanium (Sixe2x80x94Ge) layer; and the semiconductor substrate further includes a crystalline Si layer or wafer beneath the lower, unstressed, crystalline silicon-germanium (Sixe2x80x94Ge) layer.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.